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Single, 12-/14-/16-Bit nanoDACTM with 5 ppm/C On-Chip Reference in SOT-23 AD5620/AD5640/AD5660
FEATURES
Low power, single nanoDACs AD5660: 16 bits AD5640: 14 bits AD5620: 12 bits 12-bit accuracy guaranteed On-chip, 1.25 V/2.5 V, 5 ppm/C reference Tiny 8-lead SOT-23/MSOP packages Power-down to 480 nA @ 5 V, 200 nA @ 3 V 3 V/5 V single power supply Guaranteed 16-bit monotonic by design Power-on reset to zero/midscale 3 power-down functions Serial interface with Schmitt-triggered inputs Rail-to-rail operation SYNC interrupt facility
FUNCTIONAL BLOCK DIAGRAM
VREFOUT GND VDD 1.25/2.5V REF
POWER-ON RESET
AD5620/AD5640/AD5660
VFB
DAC REGISTER
REF(+) 16-BIT DAC
OUTPUT BUFFER
VOUT
INPUT CONTROL LOGIC
POWER-DOWN CONTROL LOGIC
RESISTOR NETWORK
04539-001
SYNC
SCLK
DIN
Figure 1.
APPLICATIONS
Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators
GENERAL DESCRIPTION
The AD5620/AD5640/AD5660, members of the nanoDAC family of devices, are low power, single, 12-/14-/16-bit, buffered voltage-out DACs and are guaranteed monotonic by design. The AD5620/AD5640/AD5660-1 parts include an internal, 1.25 V, 5 ppm/C reference, giving a full-scale output voltage range of 2.5 V. The AD5620/AD5640/AD5660-2-3 parts include an internal, 2.5 V, 5 ppm/C reference, giving a full-scale output voltage range of 5 V. The reference associated with each part is available at the VREFOUT pin. The parts incorporate a power-on reset circuit to ensure that the DAC output powers up to 0 V (AD5620/AD5640/AD5660-1-2) or midscale (AD5620-3 and AD5660-3) and remains there until a valid write takes place. The parts contain a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power-down mode. The power consumption is 2.5 mW at 5 V, reducing to 1 W in power-down mode. The AD5620/AD5640/AD5660 on-chip precision output amplifier allows rail-to-rail output swing to be achieved. For remote sensing applications, the output amplifier's inverting input is available to the user. The AD5620/AD5640/AD5660 use a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI(R), QSPITM, MICROWIRETM, and DSP interface standards.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. 5. 12-/14-/16-bit nanoDAC--12-bit accuracy guaranteed. On-chip, 1.25 V/2.5 V, 5 ppm/C reference. Available in 8-lead SOT-23 and 8-lead MSOP packages. Power-on reset to 0 V or midscale. 10 s settling time.
RELATED DEVICE
Part No. AD5662 Description 2.7 V to 5.5 V, 16-bit DAC in SOT-23, external reference
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
AD5620/AD5640/AD5660 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Product Highlights ........................................................................... 1 Related Device................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AD5620/AD5640/AD5660-2-3 .................................................. 3 AD5620/AD5640/AD5660-1 ...................................................... 5 Timing Characteristics ................................................................ 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 16 Theory of Operation ...................................................................... 17 D/A Section................................................................................. 17 Resistor String ............................................................................. 17 Internal Reference ...................................................................... 17 Output Amplifier........................................................................ 17 Serial Interface ............................................................................ 17 Input Shift Register .................................................................... 18 SYNC Interrupt .......................................................................... 18 Power-On Reset.......................................................................... 19 Power-Down Modes .................................................................. 19 Microprocessor Interfacing....................................................... 19 Applications..................................................................................... 21 Using an REF19x as a Power Supply for the AD5620/AD5640/AD5660 ....................................................... 21 Bipolar Operation Using the AD5660 ..................................... 21 Using the AD5660 as an Isolated, Programmable, 4 to 20 mA Process Controller ................................................. 21 Using the AD5620/AD5640/AD5660 with a Galvanically Isolated Interface...................................... 22 Power Supply Bypassing and Grounding................................ 22 Outline Dimensions ....................................................................... 23 AD5620 Ordering Guide........................................................... 23 AD5640 Ordering Guide........................................................... 24 AD5660 Ordering Guide........................................................... 24
REVISION HISTORY
9/05--Rev. 0 to Rev. A Changes to Specifications ................................................................ 5 Changes to Outline Dimensions................................................... 23 7/05--Revision 0: Initial Version
Rev. A | Page 2 of 24
AD5620/AD5640/AD5660 SPECIFICATIONS
AD5620/AD5640/AD5660-2-3
VDD = 4.5 V to 5.5 V, RL = 2 k to GND, CL = 200 pF to GND, CREFOUT = 100 nF; all specifications TMIN to TMAX, unless otherwise noted. Table 1.
Parameter STATIC PERFORMANCE 2 AD5660 Resolution Relative Accuracy Differential Nonlinearity AD5640 Resolution Relative Accuracy Differential Nonlinearity AD5620 Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Offset Error Full-Scale Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio OUTPUT CHARACTERISTICS 3 Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Output Noise Spectral Density Output Noise (0.1 Hz to 10 Hz) Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE OUTPUT Output Voltage Reference TC 3 Output Impedance A Grade 1 B Grade1 C Grade1 Unit Conditions/Comments
16 32 1 14 8 1 12 6 1 2 10 10 -0.15 -1 1.5 2 2.5 -75 0 VDD 8 10 1.5 2 10 80 45 5 0.1 0.5 30 5 2.495 2.505 10 2.8
16 16 1 14 4 1 12 1 1 2 10 10 -0.15 -1 1.5 2 2.5 -75 0 VDD 8 10 1.5 2 10 80 45 5 0.1 0.5 30 5 2.495 2.505 10 2.8
16 16 1 14 4 1 12 1 1 2 10 10 -0.15 -1 1.5 2 2.5 -75 0 VDD 8 10 1.5 2 10 80 45 5 0.1 0.5 30 5 2.495 2.505 5 20 2.8
Bits min LSB max LSB max Bits min LSB max LSB max Bits min LSB max LSB max mV typ mV max mV max % FSR typ % FSR max % FSR max V/C typ ppm typ dB typ V min V max s typ s max V/s typ nF typ nF typ nV/Hz typ V p-p typ nV-s typ nV-s typ typ mA typ s typ V min V max ppm/C typ ppm/C max k typ
Guaranteed monotonic by design
Guaranteed monotonic by design
Guaranteed monotonic by design All 0s loaded to DAC register
All 1s loaded to DAC register
Of FSR/C DAC code = midscale; VDD = 5 V 10%
1/4 to 3/4 scale change settling to 2 LSB RL = 2 k; 0 pF < CL < 200 pF 1/4 to 3/4 scale RL = RL = 2 k DAC code = midscale, 10 kHz DAC code = midscale 1 LSB change around major carry
VDD = 5 V Coming out of power-down mode; VDD = 5 V At ambient
Rev. A | Page 3 of 24
AD5620/AD5640/AD5660
Parameter LOGIC INPUTS3 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 4.5 V to 5.5 V VDD = 4.5 V to 5.5 V IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V VDD = 4.5 V to 5.5 V
1 2
A Grade 1 2 0.8 2 3 4.5 5.5 0.55 1 0.48 1
B Grade1 2 0.8 2 3 4.5 5.5 0.55 1 0.48 1
C Grade1 2 0.8 2 3 4.5 5.5 0.55 1 0.48 1
Unit A max V max V min pF typ V min V max mA typ mA max A typ A max
Conditions/Comments All digital inputs VDD = 5 V VDD = 5 V
All digital inputs at 0 V or VDD DAC active and excluding load current VIH = VDD and VIL = GND VIH = VDD and VIL = GND VIH = VDD and VIL = GND VIH = VDD and VIL = GND
Temperature range is -15C to +105C, typical at 25C. Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 128 to Code 16256); AD5620 (Code 32 to Code 4064). Output unloaded. Linearity tested with VDD = 5.5 V. If part is operated with a VDD < 5 V, the output is clamped to VDD. 3 Guaranteed by design and characterization; not production tested.
Rev. A | Page 4 of 24
AD5620/AD5640/AD5660
AD5620/AD5640/AD5660-1
VDD 1 = 2.7 V to 3.3 V, RL = 2 k to GND, CL = 200 pF to GND, CREFOUT = 100 nF; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter STATIC PERFORMANCE 3 AD5660 Resolution Relative Accuracy Differential Nonlinearity AD5640 Resolution Relative Accuracy Differential Nonlinearity AD5620 Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Offset Error Full-Scale Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio OUTPUT CHARACTERISTICS 4 Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Output Noise Spectral Density Output Noise (0.1 Hz to 10 Hz) Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE OUTPUT Output Voltage Reference TC 4 Output Impedance A Grade 2 B Grade2 C Grade2 Unit Conditions/Comments
16 32 1 14 8 1 12 6 1 2 8 9 0.15 0.85 0.85 2 2.5 -60 0 VDD 8 10 1.5 2 10 80 20 5 0.1 0.5 30 5 1.247 1.253 10 2.8
16 16 1 14 4 1 12 1 1 2 8 9 0.15 0.85 0.85 2 2.5 -60 0 VDD 8 10 1.5 2 10 80 20 5 0.1 0.5 30 5 1.247 1.253 10 2.8
16 16 1 14 4 1 12 1 1 2 8 9 0.15 0.85 0.85 2 2.5 -60
Bits min LSB max LSB max Bits min LSB max LSB max Bits min LSB max LSB max mV typ mV max mV max % FSR typ % FSR max % FSR max V/C typ ppm typ dB typ V min V max s typ s max V/s typ nF typ nF typ nV/Hz typ V p-p typ nV-s typ nV-s typ typ mA typ s typ V min V max ppm/C typ ppm/C max k typ
Guaranteed monotonic by design
Guaranteed monotonic by design
Guaranteed monotonic by design All 0s loaded to DAC register
All 1s loaded to DAC register
Of FSR/C DAC code = midscale; VDD = 3 V 10%
VDD 8 10 1.5 2 10 80 20 5 0.1 0.5 30 5 1.247 1.253 5 25 2.8
1/4 to 3/4 scale change settling to 2 LSB RL = 2 k; 0 pF < CL < 200 pF 1/4 to 3/4 scale RL = RL = 2 k DAC code = midscale, 10 kHz DAC code = midscale 1 LSB change around major carry
VDD = 3 V Coming out of power-down mode; VDD = 3 V At ambient
Rev. A | Page 5 of 24
AD5620/AD5640/AD5660
Parameter LOGIC INPUTS4 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 2.7 V to 3.3 V VDD = 2.7 V to 3.3 V IDD (All Power-Down Modes) VDD = 2.7 V to 3.3 V VDD = 2.7 V to 3.3 V
1 2
A Grade 2 1 0.8 2 3 2.7 3.3 0.55 0.65 0.2 0.25
B Grade2 1 0.8 2 3 2.7 3.3 0.55 0.65 0.2 0.25
C Grade2 1 0.8 2 3 2.7 3.3 0.55 0.65 0.2 0.25
Unit A max V max V min pF max V min V max mA typ mA max A typ A max
Conditions/Comments All digital inputs VDD = 3 V VDD = 3 V
All digital inputs at 0 V or VDD DAC active and excluding load current VIH = VDD and VIL = GND VIH = VDD and VIL = GND VIH = VDD and VIL = GND VIH = VDD and VIL = GND
Part is functional with VDD up to 5.5 V. Temperature range is -15C to +105C, typical at +25C. 3 Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 128 to Code 16256); AD5620 (Code 32 to Code 4064). Output unloaded. 4 Guaranteed by design and characterization; not production tested.
Rev. A | Page 6 of 24
AD5620/AD5640/AD5660
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
Parameter t1 1 t2 t3 t4 t5 t6 t7 t8 t9 t10
1
Limit at TMIN, TMAX VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V 50 33 13 13 13 13 13 13 5 5 4.5 4.5 0 0 50 33 13 13 0 0
Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge set-up time Data set-up time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to SCLK fall ignore SCLK falling edge to SYNC fall ignore
Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.
t10
SCLK
t1
t9
t8
SYNC
t4
t3
t2
t7
t5
DIN MSB
t6
LSB
LSB = DB0 MSB = DB23 FOR AD5660; MSB = DB15 FOR AD5620/AD5640
Figure 2. Serial Write Operation
Rev. A | Page 7 of 24
04539-002
AD5620/AD5640/AD5660 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4.
Parameter VDD to GND VOUT to GND VFB to GND VREFOUT to GND Digital Input Voltage to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) Power Dissipation SOT-23 Package (4-Layer Board) JA Thermal Impedance MSOP Package (4-Layer Board) JA Thermal Impedance JC Thermal Impedance Reflow Soldering Peak Temperature SnPb Pb-Free Rating -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -15C to +105C -65C to +150C 150C (TJ max - TA)/JA 119C/W 141C/W 44C/W 240C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 8 of 24
AD5620/AD5640/AD5660 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD 1 VREFOUT 2 VFB 3
04539-003
VOUT 4
TOP VIEW (Not to Scale)
5
SYNC
Figure 3. SOT-23 Pin Configuration
Figure 4. MSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5 Mnemonic VDD VREFOUT VFB VOUT SYNC Description Power Supply Input. These parts can operate from 2.7 V to 5.5 V. VDD should be decoupled to GND. Reference Voltage Output. Feedback Connection for the output amplifier. VFB should be connected to VOUT for normal operation. Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation. Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle for the AD5660 and the 16th clock cycle for AD5620/AD5640 unless SYNC is taken high before this edge. In this case, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. Serial Data Input. The AD5660 has a 24-bit shift register, and the AD5620/AD5640 have a 16 -bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Ground Reference Point for all circuitry on the part.
6 7 8
SCLK DIN GND
Rev. A | Page 9 of 24
04539-004
6 SCLK TOP VIEW (Not to Scale) VOUT 4 5 SYNC
AD5620/ AD5640/ AD5660
8 7
GND DIN
VDD 1 VREFOUT 2 VFB 3
AD5620/ AD5640/ AD5660
8 7 6
GND DIN SCLK
AD5620/AD5640/AD5660 TYPICAL PERFORMANCE CHARACTERISTICS
10 8 6 VDD = 5V VREFOUT = 2.5V TA = 25C
1.0 0.8 0.6
DNL ERROR (LSB)
VDD = 5V VREFOUT = 2.5V TA = 25C
INL ERROR (LSB)
4 2 0 -2 -4 -6
04539-005
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 15000 65000 16250
04539-010 04539-009 04539-008
-8 -10
10000
15000
20000
25000
30000
35000
40000
45000
50000
55000
60000
65000
5000
5000
0
0
CODE
CODE
Figure 5. INL--AD5660-2/AD5660-3
Figure 8. DNL--AD5660-2/AD5660-3
4 3 2 1 0 -1 -2
DNL ERROR (LSB) INL ERROR (LSB)
0.5
VDD = 5V VREFOUT = 2.5V TA = 25C
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3
04539-006
VDD = 5V VREFOUT = 2.5V TA = 25C
-3 -4
1250 2500 3750 5000 6250 7500 8750 10000 11250 12500 13750 15000 16250 0
-0.4 -0.5
1250 2500 3750 5000 6250 7500 8750 10000 11250 12500 13750 0
CODE
CODE
Figure 6. INL--AD5640-2/AD5640-3
Figure 9. DNL--AD5640-2/AD5640-3
1.0 0.8 0.6 VDD = 5V VREFOUT = 2.5V TA = 25C
0.20 0.15 0.10
DNL ERROR (LSB)
VDD = 5V VREFOUT = 2.5V TA = 25C
INL ERROR (LSB)
0.4 0.2 0 -0.2 -0.4
0.05 0 -0.05 -0.10
-0.6 -0.8 -1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 4000
04539-007
-0.15 -0.20 0 500 1000 1500 2000 2500 CODE 3000 3500 4000
Figure 7. INL--AD5620-2/AD6520-3
Figure 10. DNL--AD5620-2/AD6520-3
Rev. A | Page 10 of 24
AD5620/AD5640/AD5660
10 8 6 VDD = 3V VREFOUT = 1.25V TA = 25C 1.0 0.8 0.6 VDD = 3V VREFOUT = 1.25V TA = 25C
2 0 -2 -4 -6
04539-017
DNL ERROR (LSB)
INL ERROR (LSB)
4
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
04539-020
-8 -10
10000
15000
20000
25000
30000
35000
40000
45000
50000
55000
60000
65000
10000
15000
20000
25000
30000
35000
40000
45000
50000
55000
60000 15000
CODE
CODE
Figure 11. INL--AD5660-1
Figure 14. DNL--AD5660-1
4 3 2 1 0 -1 -2 VDD = 3V VREFOUT = 1.25V TA = 25C
0.5 0.4 0.3 VDD = 3V VREFOUT = 1.25V TA = 25C
DNL ERROR (LSB)
INL ERROR (LSB)
0.2 0.1 0 -0.1 -0.2 -0.3
04539-018
-0.4 -0.5
-4
10000
11250
12500
13750
CODE
CODE
Figure 12. INL--AD5640-1
Figure 15. DNL--AD5640-1
1.0 0.8 0.6 VDD = 3V VREFOUT = 1.25V TA = 25C
0.20 0.15 0.10 VDD = 3V VREFOUT = 1.25V TA = 25C
DNL ERROR (LSB)
INL ERROR (LSB)
0.4 0.2 0 -0.2 -0.4
0.05 0 -0.05 -0.10
-0.6
04539-019
-0.8 -1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 4000
-0.20 0 500 1000 1500 2000 2500 CODE 3000 3500 4000
Figure 13. INL--AD5620-1
Figure 16. DNL--AD5620-1
Rev. A | Page 11 of 24
04539-025
-0.15
16250
10000
11250
12500
13750
15000
16250
1250
2500
3750
5000
6250
7500
8750
1250
2500
3750
5000
6250
7500
8750
0
0
04539-021
-3
65000
5000
5000
0
0
AD5620/AD5640/AD5660
10 MAX INL 8 VDD = 5V 6
NUMBER OF DEVICES
160 140 120 100 80 60 40
04539-011
200 180 VDD = 5V TA = 25C
4
ERROR (LSB)
2 MAX DNL 0 -2 -4 -6 -8 -10 -15 5 MIN INL 25 45 65 TEMPERATURE (C) 85 105 MIN DNL
20 0
Figure 17. INL Error and DNL Error vs. Temperature
0.5 VDD = 5V 0.4 0.3 0.2
ERROR (% FSR)
0.50 0.40 DAC LOADED WITH FULL-SCALE SOURCING CURRENT DAC LOADED WITH ZERO-SCALE SINKING CURRENT
GAIN ERROR
ERROR VOLTAGE (V)
0.30 0.20 0.10 0 -0.10 -0.20 -0.30
04539-012
0.1 0 -0.1 -0.2 FULL-SCALE ERROR -0.3 -0.4 -0.5 -15 5 25 45 65 TEMPERATURE (C) 85 105
0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.60 0.61 0.62 0.63 0.64 0.65 0.66 0.67
IDD (mA)
Figure 20. IDD Histogram
VDD = 3V VREFOUT = 1.25V
-0.40 -0.50 -10 -8 -6 -4 -2 0 2 CURRENT (mA) 4 6 8
10
Figure 18. Gain Error and Full-Scale Error vs. Temperature
Figure 21. Headroom at Rails vs. Source and Sink
2.5 VDD = 5V 1.5 ZERO-CODE ERROR
6.00 VDD = 5V VREFOUT = 2.5V TA = 25C FULL SCALE
5.00 4.00
3/4 SCALE
0.5
ERROR (mV) VOUT (V)
3.00 MIDSCALE
-0.5
2.00 1/4 SCALE 1.00
-1.5 OFFSET ERROR -2.5
04539-013
-3.5 -15
5
25 45 65 TEMPERATURE (C)
85
105
-1.00 -30
-20
-10
0 10 CURRENT (mA)
20
30
Figure 19. Zero-Code and Offset Error vs. Temperature
Figure 22. Source and Sink Capability--AD5660-2/AD5660-3
Rev. A | Page 12 of 24
04539-023
0
ZERO SCALE
04539-022
VDD = 5V VREFOUT = 2.5V
04539-014
VDD = 3.3V
AD5620/AD5640/AD5660
4.00 VDD = 3V VREFOUT = 1.25V TA = 25C FULL SCALE 3/4 SCALE MIDSCALE 1.00 1/4 SCALE
VOUT = 909mV/DIV VDD = 5V TA = 25C FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2k AND 200pF TO GND
3.00
VOUT (V)
2.00
0
ZERO SCALE
04539-024
1
04539-028
-1.00 -30
-20
-10
0 10 CURRENT (mA)
20
30
TIME BASE = 4s/DIV
Figure 23. Source and Sink Capability--AD5660-1
Figure 26. Full-Scale Settling Time, 5 V
0.7 TA = 25C 0.6
VDD = 5V
VDD
VDD = 3V
0.5
1
IDD (mA)
0.4
VREF
2
0.3 0.2
VOUT
04539-015
0 512
10512
20512
30512 40512 CODE
50512
60512
CH1 2.00V CH2 2.00V CH3 100mV
M40.0ms
CH1
Figure 24. Supply Current vs. Code
Figure 27. Power-On Reset to 0 V--AD5660-2
1400 TA = 25C 1200
1000
VDD 1
IDD (A)
800 VDD = 5V 600 400 VDD = 3V
2 VREF
04539-016
200 0 0 1 2 VLOGIC (V) 3 4 5
3 CH1 2.00V CH2 2.00V CH3 200mV M20.0s CH1 1.88V
Figure 25. Supply Current vs. Logic Input Voltage
Figure 28. Power-On Reset to Midscale--AD5660-3
Rev. A | Page 13 of 24
04539-030
VOUT
04539-029
0.1
3
AD5620/AD5640/AD5660
1.250800 1.250600 1.250400
VDD
AMPLITUDE
1.250200 1.250000 1.249800 1.249600 1.249400 1.249200 VDD = 3V VREFOUT = 1.25V TA = 25C 13nS/SAMPLE NUMBER 1LSB CHANGE AROUND MIDSCALE (0x7FFF TO 0x8000) GLITCH IMPULSE = 0.284nV-s 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 500 550
1 2 VREF
VOUT
04539-031
1.249000 1.248800 1.248600 1.248400
CH1 1.20V CH2 1.00V CH3 100mV
M100s
CH1
1.87V
Figure 29. Power-On Reset to 0 V--AD5660-1
Figure 32. Digital-to-Analog Glitch Impulse--AD5660-1
2.500250
SCLK
VDD = 3V
2.500200 2.500150
1
AMPLITUDE
2.500100 2.500050 2.500000 2.499950 2.499900 2.499850 2.499800
VDD = 5V TA = 25C 20nS/SAMPLE NUMBER DAC LOADED WITH MIDSCALE DIGITAL FEEDTHROUGH = 0.06nV-s
3
04539-055
2.499750
04539-034
VOUT
2.499700 2.499650 2.499600 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 500 550
CH1 2.00V CH3 50.0mV
M1.00s
CH2
520mV
Figure 30. Exiting Power-Down to Midscale
Figure 33. Digital Feedthrough
2.501250 2.501000 2.500750 2.500500 2.500250
16 TA = 25C 14 VDD = 3V 12
TIME (s)
AMPLITUDE
2.500000 2.499750 2.499500 2.499250 2.499000 2.498750 2.498500 2.498250 2.498000 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 500 550 VDD = 5V VREFOUT = 2.5V TA = 25C 13nS/SAMPLE NUMBER 1LSB CHANGE AROUND MIDSCALE (0x7FFF TO 0x8000) GLITCH IMPULSE = 0.497nV-s
10
8
VDD = 5V
6
04539-032 04539-036
4 0 1 2 3 4 5 6 7 CAPACITANCE (nF) 8 9
10
Figure 31. Digital-to-Analog Glitch Impulse--AD5660-2/AD5660-3
Figure 34. Settling Time vs. Capacitive Load
Rev. A | Page 14 of 24
04539-033
3
AD5620/AD5640/AD5660
800 VDD = 5V VREFOUT = 2.5V TA = 25C DAC LOADED WITH MIDSCALE
OUTPUT NOISE (nVHz)
700 600 500 400 300 200 100 0 100
TA = 25C MIDSCALE LOADED
10V/DIV
1
VDD = 5V VREFOUT = 2.5V VDD = 3V VREFOUT = 1.25V 1000 10000 FREQUENCY (Hz) 100000
04539-037
5s/DIV
1000000
Figure 35. 0.1 Hz to 10 Hz Output Noise--AD5660-2/AD5660-3
Figure 37. Noise Spectral Density
VDD = 3V VREFOUT = 1.25V TA = 25C DAC LOADED WITH MIDSCALE
5V/DIV
1
4s/DIV
Figure 36. 0.1 Hz to 10 Hz Output Noise--AD5660-1
04539-054
Rev. A | Page 15 of 24
04539-038
AD5620/AD5640/AD5660 TERMINOLOGY
Relative Accuracy For the DAC, relative accuracy, or integral nonlinearity (INL), is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Figure 5 through Figure 7 show typical INL vs. code. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Figure 8 through Figure 10 show typical DNL vs. code. Zero-Code Error Zero-code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5620/AD5640/AD5660, because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. Figure 19 shows a plot of zero-code error vs. temperature. Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD - 1 LSB. Full-scale error is expressed as a percentage of the full-scale range. Figure 18 shows a plot of fullscale error vs. temperature. Gain Error This is a measurement of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range. Zero-Code Error Drift This is a measurement of the change in zero-code error with a change in temperature. It is expressed in V/C. Gain Temperature Coefficient This is a measurement of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/C. Offset Error Offset error is a measurement of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5660 with Code 512 loaded into the DAC register. It can be negative or positive. DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to the change in VDD for the full-scale output of the DAC. It is measured in dB. VREF is held at 2.5 V, and VDD is varied by 10%. Output Voltage Settling Time This indicates the amount of time for the output of a DAC to settle to a specified level for a 1/4 to 3/4 full-scale input change. It is measured from the 24th falling edge of SCLK. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 31 and Figure 32. Digital Feedthrough Digital feedthrough is a measurement of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s or vice versa. Noise Spectral Density This is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (voltage per Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/Hz. Figure 37 shows a plot of noise spectral density.
Rev. A | Page 16 of 24
AD5620/AD5640/AD5660 THEORY OF OPERATION
D/A SECTION
The AD5620/AD5640/AD5660 DACs are fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. The parts include an internal 1.25 V/2.5 V, 5 ppm/C reference that is internally gained up by 2. Figure 38 shows a block diagram of the DAC architecture.
VDD R VOUT OUTPUT AMPLIFIER R VFB REF (+) DAC REGISTER RESISTOR STRING REF (-)
tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
INTERNAL REFERENCE
The AD5620/AD5640/AD5660-1 parts include an internal, 1.25 V, 5 ppm/C reference, giving a full-scale output voltage of 2.5 V. The AD5620/AD5640/AD5660-2-3 parts include an internal, 2.5 V, 5 ppm/C reference, giving a full-scale output voltage of 5 V. The reference associated with each part is available at the VREFOUT pin. A buffer is required if the reference output is used to drive external loads. It is recommended that a 100 nF capacitor is placed between the reference output and GND for reference stability.
GND
Figure 38. DAC Architecture
04777-022
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. This output buffer amplifier has a gain of 2 derived from a 50 k resistor divider network in the feedback path. The inverting input of the output amplifier is available to the user, allowing for remote sensing. This VFB pin must be connected to VOUT for normal operation. It can drive a load of 2 k in parallel with 1,000 pF to GND. Figure 21 shows the source and sink capabilities of the output amplifier. The slew rate is 1.5 V/s with a 1/4 to 3/4 fullscale settling time of 10 s.
Because the input coding to the DAC is straight binary, the ideal output voltage is given by
D VOUT = 2 x VREFOUT x N 2 where: D is the decimal equivalent of the binary code that is loaded to the DAC register. 0 to 4,095 for AD5620 (12 bit) 0 to 16,383 for AD5640 (14 bit) 0 to 65,535 for AD5660 (16 bit) N is the DAC resolution.
SERIAL INTERFACE
The AD5620/AD5640/AD5660 have a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 16-bit shift register (AD5620/AD5640) or the 24-bit shift register (AD5660) on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5620/AD5640/AD5660 compatible with high speed DSPs. On the 16th falling clock edge (AD5620/ AD5640) or the 24th falling clock edge (AD5660), the last data bit is clocked in and the programmed function is executed, that is, a change in the DAC register contents and/or a change in the mode of operation is executed. At this stage, the SYNC line can be kept low or be brought high. In either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Because the SYNC buffer draws more current when VIN = 2 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation of the parts. As is mentioned previously, however, SYNC must be brought high again just before the next write sequence.
R
R
R
TO OUTPUT AMPLIFIER
R
R
04539-040
Figure 39. Resistor String
RESISTOR STRING
The resistor string section is shown in Figure 39. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is
Rev. A | Page 17 of 24
AD5620/AD5640/AD5660
INPUT SHIFT REGISTER
AD5620/AD5640
The input shift register is 16 bits wide for the AD5620/AD5640 (see Figure 40 and Figure 41). The first two bits are control bits that control which mode of operation the part is in (normal mode or any of the three power-down modes). The next 14/12 bits, respectively, are the data bits. These are transferred to the DAC register on the 16th falling edge of SCLK.
SYNC INTERRUPT
In a normal write sequence for the AD5660, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is updated on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, this acts as an interrupt to the write sequence. The shift register is reset, and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs--see Figure 43. Similarly, in a normal write sequence for the AD5620/AD5640, the SYNC line is kept low for at least 16 falling edges of SCLK, and the DAC is updated on the 16th falling edge. However, if SYNC is brought high before the 16th falling edge, this acts as an interrupt to the write sequence.
AD5660
The input shift register is 24 bits wide for the AD5660 (see Figure 42). The first six bits are don't care bits. The next two are control bits that control which mode of operation the part is in (normal mode or any of the three power-down modes). For a more complete description of the various modes, see the Power-Down Modes section. The next 16 bits are the data bits. These are transferred to the DAC register on the 24th falling edge of SCLK.
DB15 (MSB)
DB0 (LSB)
04539-041 04539-042
PD1
PD0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
DATA BITS
Figure 40. AD5620 Input Register Contents
DB15 (MSB) DB0 (LSB)
PD1
PD0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
Figure 41. AD5640 Input Register Contents
DB23 (MSB) DB0 (LSB)
04539-043
04539-044
X
X
X
X
X
X
PD1
PD0
D15
D14
D13
D12
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
Figure 42. AD5660 Input Register Contents
SCLK
SYNC
DIN
MSB
LSB
MSB
LSB
INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 16TH/24TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 16TH/24TH FALLING EDGE
Figure 43. SYNC Interrupt Facility
Rev. A | Page 18 of 24
AD5620/AD5640/AD5660
POWER-ON RESET
The AD5620/AD5640/AD5660 family contains a power-on reset circuit that controls the output voltage during power-up. The AD5620/AD5640/AD5660-1-2 DAC output powers up to 0 V, and the AD5620/AD5660-3 DAC output powers up to midscale. The output remains at this level until a valid write sequence is made to the DAC, which is useful in applications where it is important to know the state of the DAC output while it is in the process of powering up.
RESISTOR STRING DAC AMPLIFIER VOUT
POWER-DOWN CIRCUITRY
POWER-DOWN MODES
The AD5620/AD5640/AD5660 have four separate modes of operation. These modes are software-programmable by setting two bits in the control register. Table 6 and Table 7 show how the state of the bits corresponds to the operating mode of the device.
Table 6. Modes of Operation for the AD5660
DB17 0 0 1 1 DB16 0 1 0 1 AD5660 Operating Mode Normal operation Power-down modes: 1 k to GND 100 k to GND Three-state
Figure 44. Output Stage During Power-Down
The bias generator, output amplifier, reference, resistor string, and other associated linear circuitry are all shut down when power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 5 s for VDD = 5 V and VDD = 3 V. See Figure 23.
MICROPROCESSOR INTERFACING
AD5660-to-Blackfin(R) ADSP-BF53x Interface
Figure 45 shows a serial interface between the AD5660 and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5660, the setup for the interface is as follows: DT0PRI drives the DIN pin of the AD5660, while TSCLK0 drives the SCLK of the part and SYNC is driven from TFS0.
ADSP-BF53x1
Table 7. Modes of Operation for the AD5620/AD5640
DB15 0 0 1 1 DB14 0 1 0 1 AD5620/AD5640 Operating Mode Normal operation Power-down modes: 1 k to GND 100 k to GND Three-state
AD56601
TFS0 DTOPRI
SYNC DIN SCLK
04539-046
When both bits are set to 0, the part works normally with its normal power consumption of 550 A at 5 V. However, for the three power-down modes, the supply current falls to 480 nA at 5 V (200 nA at 3 V). Not only does the supply current fall, but the output stage is internally switched from the output of the amplifier to a resistor network of known values. The advantage is that the output impedance of the part is known while the part is in power-down mode. There are three options: the output is connected internally to GND through a 1 k or a 100 k resistor, or it is left open-circuited (threestated). The output stage is shown in Figure 44.
TSCLK0
1 ADDITIONAL PINS OMITTED FOR CLARITY
Figure 45. AD5660-to-Blackfin ADSP-BF53x Interface
Rev. A | Page 19 of 24
04539-045
RESISTOR NETWORK
AD5620/AD5640/AD5660
AD5660-to-68HC11/68L11 Interface
Figure 46 shows a serial interface between the AD5660 and the 68HC11/68L11 microcontroller. SCK of 68HC11/68L11 drives the SCLK of AD5660, and the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The set-up conditions for correct operation of this interface are as follows: The 68HC11/68L11 should be configured so that its CPOL bit is 0, and its CPHA bit is 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured in this way, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5660, PC7 is left low after the first eight bits are transferred, a second serial write operation is performed to the DAC, and PC7 is taken high at the end of this procedure.
68HC11/68L111
occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 output the serial data LSB first; however, the AD5660 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account.
80C51/80L511
AD56601
P3.3 TxD RxD
SYNC SCLK DIN
04539-048 04539-049
1 ADDITIONAL PINS OMITTED FOR CLARITY
Figure 47. AD5660-to-80C51/80L51 Interface
AD5660-to-MICROWIRE Interface
AD56601
PC7 SCK MOSI
SYNC SCLK DIN
04539-047
Figure 48 shows an interface between the AD5660 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5660 on the rising edge of the SK.
MICROWIRE1
AD56601
1 ADDITIONAL PINS OMITTED FOR CLARITY
Figure 46. AD5660-to-68HC11/68L11 Interface
CS SK SO
SYNC SCLK DIN
AD5660-to-80C51/80L51 Interface
Figure 47 shows a serial interface between the AD5660 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/80L51 drives SCLK of the AD5660, and RxD drives the serial data line of the part. The SYNC signal is again derived from a bit-programmable pin on the port. In this case, Port Line P3.3 is used. When data is to be transmitted to the AD5660, P3.3 is taken low. The 80C51/80L51 transmit data only in 8-bit bytes; therefore, only eight falling clock edges
1 ADDITIONAL PINS OMITTED FOR CLARITY
Figure 48. AD5660-to-MICROWIRE Interface
Rev. A | Page 20 of 24
AD5620/AD5640/AD5660 APPLICATIONS
USING AN REF19x AS A POWER SUPPLY FOR THE AD5620/AD5640/AD5660
Because the supply current required by the AD5620/AD5640/ AD5660 is extremely low, an alternative option is to use a REF19x voltage reference (REF195 for 5 V or REF193 for 3 V) to supply the required voltage to the part--see Figure 49. This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V or 3 V, for example, 15 V. The REF19x outputs a steady supply voltage for the AD5620/ AD5640/AD5660. If the low dropout REF195 is used, the current it needs to supply to the AD5660 is 500 A. This is with no load on the output of the DAC. When the DAC output is loaded, the REF195 also must supply the current to the load. The total current required (with a 5 k load on the DAC output) is 500 A + (5 V/5 k) = 1.5 mA The load regulation of the REF195 is typically 2 ppm/mA, which results in an error of 3 ppm (15 V) for the 1.5 mA current drawn from it. This corresponds to a 0.197 LSB error for the AD5660.
15V 5V
+5V R1 10k R2 10k +5V
VDD 10F 0.1F
VFB VOUT
AD820/ OP295
5V
AD5660
-5V
3-WIRE SERIAL INTERFACE
Figure 50. Bipolar Operation with the AD5660
USING THE AD5660 AS AN ISOLATED, PROGRAMMABLE, 4 TO 20 mA PROCESS CONTROLLER
In many process-control system applications, 2-wire current transmitters are used to transmit analog signals through noisy environments. These current transmitters use a zero-scale signal current of 4 mA to power the signal conditioning circuitry of the transmitter. The full-scale output signal in these transmitters is 20 mA. The converse approach to process control can also be used, in which a low-power, programmable current source is used to control remotely located sensors or devices in the loop. A circuit that performs this function is shown in Figure 51. Using the AD5660 as the controller, the circuit provides a programmable output current of 4 to 20 mA, proportional to the digital code of the DAC. Biasing for the controller is provided by the ADR02 and requires no external trim for two reasons: first, the ADR02's tight initial output voltage tolerance, and second, the low supply current consumption of both the AD8627 and the AD5660. The entire circuit, including optocouplers, consumes less than 3 mA from the total budget of 4 mA. The AD8627 regulates the output current to satisfy the current summation at the noninverting node of the AD8627. IOUT = 1/R7 (VDAC x R3/R1 + VREF x R3/R2) For the values shown in Figure 51, IOUT = 0.2435 A x D + 4 mA where D = 0 D 65,535, giving a full-scale output current of 20 mA when the AD5660's digital code equals 0xFFFF. Offset trim at 4 mA is provided by P2, and P1 provides the circuit gain trim at 20 mA. These two trims do not interact because the noninverting input of the AD8627 is at virtual ground. The Schottky diode, D1, is required in this circuit to prevent loop supply power-on transients from pulling the noninverting input of the AD8627 more than 300 mV below its inverting input. Without this diode, such transients could cause phase reversal
REF195
Figure 49. REF195 as the Power Supply to the AD5660
BIPOLAR OPERATION USING THE AD5660
The AD5660 is designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 50. Figure 50 gives an output voltage range of 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. The output voltage for any input code can be calculated as
D R1 + R2 R2 VO = VDD x x - VDD x 65536 R1 R1
where D represents the input code in decimal (0 to 65,535). When VDD = 5 V, R1 = R2 = 10 k, 10 x D VO = -5 V 65536 This results in an output voltage range of 5 V, with 0x0000 corresponding to a -5 V output and 0xFFFF corresponding to a +5 V output.
04539-050
3-WIRE SERIAL INTERFACE
SYNC SCLK DIN
AD5660
VOUT = 0V TO 5V
Rev. A | Page 21 of 24
04539-051
AD5620/AD5640/AD5660
of the AD8627 and possible latch-up of the controller. The loop supply voltage compliance of the circuit is limited by the maximum applied input voltage to the ADR02 and is from 12 V to 40 V.
ADR02
R2 18.5k P2 4mA ADJUST VLOOP 12V TO 36V
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5620/ AD5640/AD5660 should have separate analog and digital sections, each having its own area of the board. If the AD5620/ AD5640/AD5660 are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5620/AD5640/AD5660. The power supply to the AD5620/AD5640/AD5660 should be bypassed with 10 F and 0.1 F capacitors. The capacitors should be as close as physically possible to the device, with the 0.1 F capacitor ideally right up against the device. The 10 F capacitors are the tantalum bead type. It is important that the 0.1 F capacitor has a low effective series resistance (ESR) and low effective series inductance (ESI), such as is typical of common ceramic types of capacitors. This 0.1 F capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other components with fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. The best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.
SERIAL LOAD
AD5660
R1 4.7k
P1 20mA ADJUST R3 1.5k
AD8627 R6 3.3k
Q1 2N3904
D1
4-20mA
04539-052
RL R7 100
Figure 51. Programmable 4 to 20 mA Process Controller
USING THE AD5620/AD5640/AD5660 WITH A GALVANICALLY ISOLATED INTERFACE
For process-control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from hazardous common-mode voltages that might occur in the area where the DAC is functioning. The iCoupler(R) provides isolation in excess of 2.5 kV. The AD5620/AD5640/AD5660 use a 3-wire serial logic interface; therefore, the ADuM1300 3-channel digital isolator provides the required isolation (see Figure 52). The power supply to the part also must be isolated, which is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5620/AD5640/AD5660.
5V REGULATOR POWER 10F 0.1F
VDD SCLK V1A VOA SCLK
ADuM1300
AD56x0
VOB SYNC VOUT
SDI
V1B
DATA
V1C
VOC
DIN
04539-053
GND
Figure 52. AD5620/AD5640/AD5660 with a Galvanically Isolated Interface
Rev. A | Page 22 of 24
AD5620/AD5640/AD5660 OUTLINE DIMENSIONS
2.90 BSC 3.20 3.00 2.80
5
8
7
6
1.60 BSC
1 2 3 4
2.80 BSC
3.20 3.00 2.80
8
5
1
5.15 4.90 4.65
4
PIN 1 INDICATOR 0.65 BSC 1.30 1.15 0.90 1.95 BSC 0.95 0.85 0.75 1.45 MAX 0.38 0.22 0.22 0.08 8 4 0 0.60 0.45 0.30 0.15 0.00 0.38 0.22 SEATING PLANE PIN 1 0.65 BSC 1.10 MAX 8 0 0.80 0.60 0.40
0.23 0.08
0.15 MAX
SEATING PLANE
COPLANARITY 0.10
COMPLIANT TO JEDEC STANDARDS MO-178-BA
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 53. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters
Figure 54. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
AD5620 ORDERING GUIDE
Model AD5620ARJ-1500RL7 AD5620ARJ-1REEL7 AD5620ARJ-2500RL7 AD5620ARJ-2REEL7 AD5620BRJ-1500RL7 AD5620BRJ-1REEL7 AD5620BRJ-2500RL7 AD5620BRJ-2REEL7 AD5620CRM-1 AD5620CRM-1REEL7 AD5620CRM-2 AD5620CRM-2REEL7 AD5620CRM-3 AD5620CRM-3REEL7 EVAL-AD5620EB Temp. Range -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C Package Description 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Evaluation Board Package Option RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 Branding D2K D2K D2L D2L D2H D2H D2J D2J D2M D2M D2N D2N D2P D2P Power-On Reset to Code Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Midscale Midscale Accuracy 6 LSB INL 6 LSB INL 6 LSB INL 6 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL Internal Reference 1.25 V 1.25 V 2.5 V 2.5 V 1.25 V 1.25 V 2.5 V 2.5 V 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V
Rev. A | Page 23 of 24
AD5620/AD5640/AD5660
AD5640 ORDERING GUIDE
Model AD5640ARJ-2500RL7 AD5640ARJ-2REEL7 AD5640BRJ-1500RL7 AD5640BRJ-1REEL7 AD5640BRJ-2500RL7 AD5640BRJ-2REEL7 AD5640CRM-1 AD5640CRM-1REEL7 AD5640CRM-2 AD5640CRM-2REEL7 EVAL-AD5640EB Temp. Range -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C Package Description 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Evaluation Board Package Option RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RM-8 RM-8 RM-8 RM-8 Branding D2T D2T D2Q D2Q D2R D2R D2U D2U D2V D2V Power-On Reset to Code Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Accuracy 8 LSB INL 8 LSB INL 4 LSB INL 4 LSB INL 4 LSB INL 4 LSB INL 4 LSB INL 4 LSB INL 4 LSB INL 4 LSB INL Internal Reference 2.5 V 2.5 V 1.25 V 1.25 V 2.5 V 2.5 V 1.25 V 1.25 V 2.5 V 2.5 V
AD5660 ORDERING GUIDE
Model AD5660ARJ-1500RL7 AD5660ARJ-1REEL7 AD5660ARJ-2500RL7 AD5660ARJ-2REEL7 AD5660ARJ-3500RL7 AD5660ARJ-3REEL7 AD5660BRJ-1500RL7 AD5660BRJ-1REEL7 AD5660BRJ-2500RL7 AD5660BRJ-2REEL7 AD5660BRJ-3500RL7 AD5660BRJ-3REEL7 AD5660CRM-1 AD5660CRM-1REEL7 AD5660CRM-2 AD5660CRM-2REEL7 AD5660CRM-3 AD5660CRM-3REEL7 EVAL-AD5660EB Temp. Range -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C -15C to +105C Package Description 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Evaluation Board Package Option RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 Branding D30 D30 D31 D31 D32 D32 D2X D2X D2Y D2Y D2Z D2Z D33 D33 D34 D34 D35 D35 Power-On Reset to Code Zero Zero Zero Zero Midscale Midscale Zero Zero Zero Zero Midscale Midscale Zero Zero Zero Zero Midscale Midscale Accuracy 32 LSB INL 32 LSB INL 32 LSB INL 32 LSB INL 32 LSB INL 32 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL Internal Reference 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04539-0-9/05(A)
Rev. A | Page 24 of 24

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